The invention relates generally to transmitting binary data over a data transmission line and more precisely to transmitting binary data over a data transmission line with minimized digital inter-symbol interference.
As illustrated in FIG. 1, data is typically transmitted back and forth between a host computer system 10 and peripheral devices, such as disk drive 5, tape drive 6, or printer 7, over a data bus 15. The data bus 15 couples the host computer system 10 and the peripheral devices together and enables the exchange of data between the system and the devices. One type of data bus is a Small Computer System Interconnect (SCSI) data bus. A SCSI data bus can be configured in different ways and has several modes of operation. One configuration and mode of operation is known as SCSI wide bus which includes a sixteen bit data bus with associated control signals such as Busy (BSY), Select (SEL), Control/Data (C/D), Input/Output (I/O), Message (MSG), Request (REQ), Acknowledge (ACK), Attention (ATN), and Reset (RST). The SCSI data bus 15 is connected to the host computer system 10 via a host adapter 12 and is connected to disk drive 5, tape drive 6, and printer 7 via disk controller 8, tape controller 9, and printer controller 11, respectively. The device controller is matched to the specific type of device connected to the SCSI bus as shown in FIG. 1. The data bus 15 may be configured to include a plurality of peripheral devices daisy chained together, where both the host computer system 10 and the last device connected to the data bus 15 (furthest from the host) are terminated with a bus terminator 16. The bus terminator 16 includes circuitry for regulating the maximum and the minimum voltage levels on the data bus 15.
Referring to FIGS. 2A and 2B, the maximum and minimum voltage thresholds for data detection (V-one and V-zero) are sensed by data detection circuitry 13. Each threshold is a fixed d.c. voltage level connected to a signal line of the data bus 15, which is driven by driver circuitry 14. This fixed d.c. threshold level is typically defined between the terminator voltage boundaries (+V-term and xe2x88x92V-term). Both the host adapter and the device controllers contain driver circuitry 14 for driving, and data detection circuitry 13 for receiving, the data and logic circuits (not shown in FIG. 2A) for directing data flow and processing operations.
When information is transferred between the host computer system and any one of the plurality of peripheral devices, a handshaking protocol is used to initiate data requests and acknowledge that such requests have been completed. A REQ control signal may be asserted by an initiating device to request that the target either write or read data to/from the initiating device. An ACK control signal may be asserted by the target device to acknowledge that the target device successfully sent or received data.
A problem can occur when the SCSI data bus idles with no data transfers for a prolonged period of time. In this instance the voltage level on the data bus will rise to the maximum voltage value defined by the bus terminators, called herein the xe2x80x9cquiescent negated voltage level.xe2x80x9d When a REQ is asserted, the REQ control circuitry provides a predetermined fixed window of time for the REQ to be sensed by the data detection circuitry before subsequent REQs are asserted. Since the bus voltage is at the quiescent negated voltage level during prolonged idles, the REQ must make a larger signal level swing than during synchronous operation in order to reach a level capable of being sensed as a REQ by the data detection circuitry. In one failure mode, there is insufficient time for the REQ signal to be sensed by the data detection circuitry during a first assertion of REQ before a subsequent REQ is asserted. Consequently, REQ data transmitted on other lines of the data bus during the first REQ pulse may not be sensed correctly by the data detection circuitry and may be lost. A second failure mode occurs when the REQ signal is not sensed at all by the data detection circuit within predetermined time constraints. These failure modes are hereby defined as digital control inter-symbol interference, i.e., xe2x80x9ccontrol ISI.xe2x80x9d
The above described problems which can occur during the first REQ assertion are not relevant to subsequent REQs because the data bus voltage level is no longer at the quiescent negated voltage level and thus subsequently transmitted REQs do not require as large a voltage swing before being sensed by the data detection circuitry.
Referring to FIG. 3, a similar problem occurs when the user data signal is unchanged (all zeros or ones) for a prolonged period of time. A prolonged unchanged user data signal allows the user data voltage level to approach the quiescent negated voltage level. Subsequent transitions in the user data signal from the quiescent negated voltage level require a large voltage swing in the data signal in order to be sensed by the data detection circuitry. Again, there is a fixed period of time for these data signal transitions to be sensed by the data detection circuitry before another signal transition is asserted. However, this period of time is often insufficient for the first data signal transition to be sensed by the data detection circuitry, thereby causing the data defined within this first large data signal transition to be lost. This loss of user data occurring within the first user data transition is hereby defined as digital data inter-symbol interference (xe2x80x9cdata ISIxe2x80x9d).
In transmitting data over a data bus, the trend is to increase the frequency at which information can be transferred over the data bus. However, an increase in data frequency causes a proportional decrease in the time period allowable for control and data pulses to be sensed by the data detection circuitry. Therefore, as data transmission frequencies are increased, there is a corresponding increase in both control ISI as well as data ISI as defined above. Minimizing both control and data ISI is thus highly desirable.
An object of the present invention is to transmit data over a data bus with minimized digital control inter-symbol interference.
Another object of the present invention is to transmit data over a data bus with minimized digital data inter-symbol interference.
A first embodiment of the present invention comprises a method for transmitting data from a sending device (sender) to a receiving device (receiver) via a data bus in a manner to minimize control and data inter-symbol interference. The method comprises the steps of executing a start data transfer command, waiting for a FIFO register to contain data, the FIFO register being coupled to a peripheral device, determining when the FIFO register is holding the data, driving the data held in the FIFO register onto the data bus, inverting the data previously driven onto the data bus to reduce the quiescent negated voltage level of the data bus, driving the inverted data onto the data bus, pausing for a predetermined period of time (t3), driving true data onto the data bus, pausing for a predetermined period of time (t1), asserting a REQ control signal, and pausing a predetermined period of time, (t2), for the data to be sensed by the data detection circuitry. The step of pausing for the predetermined period of time, t2, provides the data detection circuitry additional time to sense the data being transmitted on the data bus, thereby minimizing digital control inter-symbol interference during data transmission from the sender to the receiver.
This method transmits data over the data bus with minimized digital control and data inter-symbol interference because the voltage level on the data bus is not permitted to reach the quiescent negated voltage level (the bus terminator voltage level) before a transition occurs. Even after a prolonged period of time where data signals transmitted over the data bus have remained constant, an abrupt transition is not subjected to the lengthy transition necessitated by the bus floating at the quiescent negated voltage level. Moreover, additional time is provided for the first REQ pulse to be detected before subsequent REQ pulses are asserted. Accordingly, the first level transition occurring after the prolonged unchanged data transmission level is detected by the data detection circuitry within predefined data detection circuitry time constraints.
These and other objects, advantages, aspects and features of the present invention will be more fully understood and appreciated upon consideration of the following detailed description of a preferred embodiment, presented in conjunction with the accompanying drawings.